7#ifndef KIS_XSIMD_ARCH_HPP
8#define KIS_XSIMD_ARCH_HPP
18#define Scalar 0x00100000
19#define SSE2 0x00200000
20#define SSE3 0x00300000
21#define SSSE3 0x00400000
22#define SSE4_1 0x00500000
23#define SSE4_2 0x00600000
24#define FMA4 0x00700000
26#define AVX2 0x00900000
27#define AVX512F 0x00A00000
28#define AVX512BW 0x00B00000
29#define AVX512CD 0x00C00000
30#define AVX512DQ 0x00D00000
31#define NEON 0x10100000
32#define NEON64 0x10200000
36#define Intel_Architecture 0x00000000
37#define Arm_Architecture 0x10000000
39#define IMPL_MASK 0xFFF00000
40#define PLATFORM_MASK 0xF0000000
44#if defined(XSIMD_IMPL) && (XSIMD_IMPL & IMPL_MASK) == Scalar
46#elif !defined(XSIMD_IMPL)
48#elif (XSIMD_IMPL & IMPL_MASK) == SSE2
50#elif (XSIMD_IMPL & IMPL_MASK) == SSE3
52#elif (XSIMD_IMPL & IMPL_MASK) == SSSE3
54#elif (XSIMD_IMPL & IMPL_MASK) == SSE4_1
56#elif (XSIMD_IMPL & IMPL_MASK) == SSE4_2
62#elif (XSIMD_IMPL & IMPL_MASK) == FMA4
64#elif (XSIMD_IMPL & IMPL_MASK) == AVX
70#elif (XSIMD_IMPL & IMPL_MASK) == AVX2
76#elif (XSIMD_IMPL & IMPL_MASK) == AVX512F
78#elif (XSIMD_IMPL & IMPL_MASK) == AVX512CD
80#elif (XSIMD_IMPL & IMPL_MASK) == AVX512DQ
82#elif (XSIMD_IMPL & IMPL_MASK) == AVX512BW
84#elif (XSIMD_IMPL & IMPL_MASK) == NEON
86#elif (XSIMD_IMPL & IMPL_MASK) == NEON64
96#if !defined(XSIMD_IMPL) || defined(XSIMD_IMPL) && (XSIMD_IMPL & IMPL_MASK) == Scalar
97#define XSIMD_UNIVERSAL_BUILD_PASS 3
98#elif XSIMD_WITH_SSE2 && (XSIMD_IMPL & PLATFORM_MASK) == Intel_Architecture
99#define XSIMD_UNIVERSAL_BUILD_PASS 2
100#elif (XSIMD_WITH_NEON || XSIMD_WITH_NEON64) && (XSIMD_IMPL & PLATFORM_MASK) == Arm_Architecture
101#define XSIMD_UNIVERSAL_BUILD_PASS 1
104#ifndef XSIMD_UNIVERSAL_BUILD_PASS
105#define XSIMD_UNIVERSAL_BUILD_PASS 0
default_arch current_arch